The present invention relates to a manufacturing method for a semiconductor integrated circuit device, and more particularly to such a method effective when applied to a semiconductor integrated circuit device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a salicide (self-aligned silicide) structure.
As one of the techniques for realizing a high-speed operation of MISFET, there is known a so-called salicide technique such that a high-melting point metal silicide layer having a low resistance is formed on the surfaces of a gate electrode and source and drain regions. Such a salicide technique is described in Japanese Patent Laid-open No. 61-150216 or U.S. Pat. No. 5,081,066, for example.
The method of forming a salicide as described in Japanese Patent Laid-open No. 61-150216 will now be described. First, a polysilicon film deposited over a semiconductor substrate is patterned to form a gate electrode of a MISFET, and then a side wall spacer of silicon oxide is formed on the side wall of the gate electrode. Then, an impurity is introduced into the semiconductor substrate by an ion implantation process with the gate electrode and the side wall spacer being used as a mask, thereby forming source and drain regions in the semiconductor substrate on both sides of the gate electrode.
Then, an insulating film (gate insulating film) on the surfaces of the source and drain regions is removed by etching, and then a titanium (Ti) film is deposited over the surface of the semiconductor substrate by a sputtering process. Then, the semiconductor substrate is annealed to form a Ti silicide layer in the interface between the gate electrode (polysilicon) and the Ti film and in the interface between the source and drain regions (single crystal of silicon) and the Ti film.
The annealing for forming the Ti silicide layer is performed at a relatively low temperature of about 400.degree. to 600.degree. C. in an atmosphere of inert gas. Such a low-temperature annealing is due to the fact that if the annealing is performed at a high temperature, silicon (Si) in the substrate is attracted into the Ti film to also form a silicide layer on the side wall spacer or there occurs a reaction of the Ti film with the silicon oxide film (the side wall spacer), resulting in short-circuit between the gate electrode and the source and drain regions through the Ti silicide layer on the side wall spacer.
However, the Ti silicide (TiSi.sub.x ; x&lt;2) layer formed by the low-temperature annealing mentioned above has a high resistance (a sheet resistance of about 30 to 40 .OMEGA./sq. at an annealing temperature of 500.degree. C.), which cannot be put to practical use. Accordingly, an unreacted portion of the Ti film left on the side wall spacer and the like is removed by wet etching, and then second annealing is performed at a high temperature of 600.degree. C. or more in an atmosphere of inert gas to reduce the resistance of the Ti silicide layer on the gate electrode and the source and drain regions, thereby obtaining a Ti silicide (TiSi.sub.2) layer having a sheet resistance of about 5 to 10 .OMEGA./sq.
Thus in such a conventional salicide process of forming a silicide layer on the gate electrode and the source and drain regions in the MISFET, annealing is performed twice at different temperatures to form a silicide layer having a low resistance.
An n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the polysilicon film forming the gate electrode of the MISFET, so as to reduce the resistance of the gate electrode. The introduction of P or As is performed simultaneously with the deposition of the polysilicon film.
However, if the n-type impurity is introduced at a high concentration into the polysilicon film to reduce the resistance of the gate electrode, the silicide reaction in the interface between the gate electrode (polysilicon film) and the Ti film as mentioned above is hindered. Specifically, when the concentration of the n-type impurity in the polysilicon film is about 2.times.10.sup.20 atoms/cm.sup.3 or more during the deposition, the first silicide reaction (Ti+Si.fwdarw.TiSi.sub.x ; x&lt;2) is progressed, but the second silicide reaction (TiSi.sub.x .fwdarw.TiSi.sub.2) is hindered from being progressed. Accordingly, even when the high-temperature annealing is performed, the silicide layer (TiSi.sub.x) having a high resistance remains on the gate electrode, causing an increase in sheet resistance (.rho.s) of the gate electrode.
Further, the sheet resistance of the gate electrode largely varies with the annealing temperature in performing the second silicide reaction (TiSi.sub.x .fwdarw.TiSi.sub.2). That is, if the annealing temperature at this time is low, the second silicide reaction is not enough progressed. Accordingly, in a heat treatment process (e.g., reflow and densification of an interlayer insulating film) to be performed after the annealing, there occurs agglomeration in the silicide layer to increase the sheet resistance. Conversely, if the annealing temperature is excessively high, there occurs agglomeration during the course of the silicide reaction to yet increase the sheet resistance.
On the other hand, if the concentration of the n-type impurity in the polysilicon film forming the gate electrode is reduced to avoid the above problem, there occurs another problem such that when a positive voltage is applied to the gate electrode with the semiconductor substrate (well) grounded, a depletion layer is formed in the gate electrode, with the result that an effective thickness of the gate electrode is increased to cause a decrease in drain current in the MISFET.